This invention relates in general to silicon-on-sapphire technology, and more particularly, to a technique for threshold control over the edges of metal-oxide-semiconductor devices fabricated on an insulating substrate such as sapphire or spinel.
Metal-oxide-semiconductor (MOS) devices fabricated on silicon-on-sapphire (SOS) offer higher speed, simplified circuit design, and improved radiation hardness in comparison with bulk MOS technology. The very good dielectric isolation between adjacent devices provided by the sapphire insulating substrate permits high packing density for MOS/SOS circuits.
In conventional SOS processing, a layer of silicon is epitaxially deposited on a sapphire substrate and silicon is etched away from the region between adjacent devices to form silicon islands on the substrate. Typically, the top surface of the silicon islands has a &lt;100&gt; Miller indices orientation, however, as a consequence of the nature of the silicon etching techniques, the edges of the islands (where the etching was performed) have different orientations. For example, if a preferential silicon etch was used, the edges of the islands will have &lt;111&gt; Miller indices.
The different orientation of the edges results in a density of surface states and fixed charges in the edges different from that in the top surface. Consequently, the channel edges may conduct a voltage lower than the threshold voltage of the top surface. This conduction between the source and drain in the channel edges (2 edges per transistor) at a voltage lower than the threshold voltage of the top surface is undesirable since the edges function as parasitic transistors which turn on before the main transistor (top surface). This problem usually manifests itself in n-channel devices.
Channel-edge conduction problems have been controlled by fabricating edgeless devices of circular geometry or by heavily doping the channel edges so that they cannot be inverted. The circular edgeless devices are more complex to construct and cannot be made in the small geometries of rectilinear devices; thus they have a lower packing density. The prior art techniques of doping the channel edges are unsatisfactory for small-geometry rectilinear devices because the top surface of the channel is masked in a separate step to protect it while the edges are doped. In devices with a small channel width, the processing error necessarily involved in masking the top surface results in a significant portion of the top surface being doped. This in turn significantly lowers the active area of the transistor. For example, in a device having a five-micron channel width, if one micron of the top surface is doped while doping each edge, the current available from the device will be reduced by forty percent.